
polym-04:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004007c8 <_init>:
  4007c8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4007cc:	910003fd 	mov	x29, sp
  4007d0:	94000046 	bl	4008e8 <call_weak_fn>
  4007d4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4007d8:	d65f03c0 	ret

Disassembly of section .plt:

00000000004007e0 <.plt>:
  4007e0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4007e4:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0xfd68>
  4007e8:	f947fe11 	ldr	x17, [x16, #4088]
  4007ec:	913fe210 	add	x16, x16, #0xff8
  4007f0:	d61f0220 	br	x17
  4007f4:	d503201f 	nop
  4007f8:	d503201f 	nop
  4007fc:	d503201f 	nop

0000000000400800 <__libc_start_main@plt>:
  400800:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400804:	f9400211 	ldr	x17, [x16]
  400808:	91000210 	add	x16, x16, #0x0
  40080c:	d61f0220 	br	x17

0000000000400810 <_ZdlPvm@plt>:
  400810:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400814:	f9400611 	ldr	x17, [x16, #8]
  400818:	91002210 	add	x16, x16, #0x8
  40081c:	d61f0220 	br	x17

0000000000400820 <__cxa_atexit@plt>:
  400820:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400824:	f9400a11 	ldr	x17, [x16, #16]
  400828:	91004210 	add	x16, x16, #0x10
  40082c:	d61f0220 	br	x17

0000000000400830 <_ZNSt8ios_base4InitC1Ev@plt>:
  400830:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400834:	f9400e11 	ldr	x17, [x16, #24]
  400838:	91006210 	add	x16, x16, #0x18
  40083c:	d61f0220 	br	x17

0000000000400840 <abort@plt>:
  400840:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400844:	f9401211 	ldr	x17, [x16, #32]
  400848:	91008210 	add	x16, x16, #0x20
  40084c:	d61f0220 	br	x17

0000000000400850 <__gxx_personality_v0@plt>:
  400850:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400854:	f9401611 	ldr	x17, [x16, #40]
  400858:	9100a210 	add	x16, x16, #0x28
  40085c:	d61f0220 	br	x17

0000000000400860 <_Unwind_Resume@plt>:
  400860:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400864:	f9401a11 	ldr	x17, [x16, #48]
  400868:	9100c210 	add	x16, x16, #0x30
  40086c:	d61f0220 	br	x17

0000000000400870 <__gmon_start__@plt>:
  400870:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400874:	f9401e11 	ldr	x17, [x16, #56]
  400878:	9100e210 	add	x16, x16, #0x38
  40087c:	d61f0220 	br	x17

0000000000400880 <printf@plt>:
  400880:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400884:	f9402211 	ldr	x17, [x16, #64]
  400888:	91010210 	add	x16, x16, #0x40
  40088c:	d61f0220 	br	x17

0000000000400890 <_ZNSt8ios_base4InitD1Ev@plt>:
  400890:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400894:	f9402611 	ldr	x17, [x16, #72]
  400898:	91012210 	add	x16, x16, #0x48
  40089c:	d61f0220 	br	x17

Disassembly of section .text:

00000000004008a0 <_start>:
  4008a0:	d280001d 	mov	x29, #0x0                   	// #0
  4008a4:	d280001e 	mov	x30, #0x0                   	// #0
  4008a8:	aa0003e5 	mov	x5, x0
  4008ac:	f94003e1 	ldr	x1, [sp]
  4008b0:	910023e2 	add	x2, sp, #0x8
  4008b4:	910003e6 	mov	x6, sp
  4008b8:	580000c0 	ldr	x0, 4008d0 <_start+0x30>
  4008bc:	580000e3 	ldr	x3, 4008d8 <_start+0x38>
  4008c0:	58000104 	ldr	x4, 4008e0 <_start+0x40>
  4008c4:	97ffffcf 	bl	400800 <__libc_start_main@plt>
  4008c8:	97ffffde 	bl	400840 <abort@plt>
  4008cc:	00000000 	.inst	0x00000000 ; undefined
  4008d0:	00400a78 	.word	0x00400a78
  4008d4:	00000000 	.word	0x00000000
  4008d8:	00400da0 	.word	0x00400da0
  4008dc:	00000000 	.word	0x00000000
  4008e0:	00400e20 	.word	0x00400e20
  4008e4:	00000000 	.word	0x00000000

00000000004008e8 <call_weak_fn>:
  4008e8:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0xfd68>
  4008ec:	f947f000 	ldr	x0, [x0, #4064]
  4008f0:	b4000040 	cbz	x0, 4008f8 <call_weak_fn+0x10>
  4008f4:	17ffffdf 	b	400870 <__gmon_start__@plt>
  4008f8:	d65f03c0 	ret
  4008fc:	00000000 	.inst	0x00000000 ; undefined

0000000000400900 <deregister_tm_clones>:
  400900:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400904:	9101a000 	add	x0, x0, #0x68
  400908:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  40090c:	9101a021 	add	x1, x1, #0x68
  400910:	eb00003f 	cmp	x1, x0
  400914:	540000a0 	b.eq	400928 <deregister_tm_clones+0x28>  // b.none
  400918:	90000001 	adrp	x1, 400000 <_init-0x7c8>
  40091c:	f9472021 	ldr	x1, [x1, #3648]
  400920:	b4000041 	cbz	x1, 400928 <deregister_tm_clones+0x28>
  400924:	d61f0020 	br	x1
  400928:	d65f03c0 	ret
  40092c:	d503201f 	nop

0000000000400930 <register_tm_clones>:
  400930:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400934:	9101a000 	add	x0, x0, #0x68
  400938:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  40093c:	9101a021 	add	x1, x1, #0x68
  400940:	cb000021 	sub	x1, x1, x0
  400944:	9343fc21 	asr	x1, x1, #3
  400948:	8b41fc21 	add	x1, x1, x1, lsr #63
  40094c:	9341fc21 	asr	x1, x1, #1
  400950:	b40000a1 	cbz	x1, 400964 <register_tm_clones+0x34>
  400954:	90000002 	adrp	x2, 400000 <_init-0x7c8>
  400958:	f9472442 	ldr	x2, [x2, #3656]
  40095c:	b4000042 	cbz	x2, 400964 <register_tm_clones+0x34>
  400960:	d61f0040 	br	x2
  400964:	d65f03c0 	ret

0000000000400968 <__do_global_dtors_aux>:
  400968:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40096c:	910003fd 	mov	x29, sp
  400970:	f9000bf3 	str	x19, [sp, #16]
  400974:	d0000093 	adrp	x19, 412000 <__libc_start_main@GLIBC_2.17>
  400978:	3941a260 	ldrb	w0, [x19, #104]
  40097c:	35000080 	cbnz	w0, 40098c <__do_global_dtors_aux+0x24>
  400980:	97ffffe0 	bl	400900 <deregister_tm_clones>
  400984:	52800020 	mov	w0, #0x1                   	// #1
  400988:	3901a260 	strb	w0, [x19, #104]
  40098c:	f9400bf3 	ldr	x19, [sp, #16]
  400990:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400994:	d65f03c0 	ret

0000000000400998 <frame_dummy>:
  400998:	17ffffe6 	b	400930 <register_tm_clones>

000000000040099c <_Z9TestBoundv>:
  40099c:	a9b87bfd 	stp	x29, x30, [sp, #-128]!
  4009a0:	910003fd 	mov	x29, sp
  4009a4:	f9000bf3 	str	x19, [sp, #16]
  4009a8:	9101a3a0 	add	x0, x29, #0x68
  4009ac:	9400005a 	bl	400b14 <_ZN4BaseC1Ev>
  4009b0:	910143a0 	add	x0, x29, #0x50
  4009b4:	94000087 	bl	400bd0 <_ZN4Sub1C1Ev>
  4009b8:	9100e3a0 	add	x0, x29, #0x38
  4009bc:	940000a9 	bl	400c60 <_ZN4Sub2C1Ev>
  4009c0:	9101a3a0 	add	x0, x29, #0x68
  4009c4:	f90013a0 	str	x0, [x29, #32]
  4009c8:	910143a0 	add	x0, x29, #0x50
  4009cc:	f90017a0 	str	x0, [x29, #40]
  4009d0:	9100e3a0 	add	x0, x29, #0x38
  4009d4:	f9001ba0 	str	x0, [x29, #48]
  4009d8:	b9007fbf 	str	wzr, [x29, #124]
  4009dc:	b9407fa0 	ldr	w0, [x29, #124]
  4009e0:	7100081f 	cmp	w0, #0x2
  4009e4:	5400024c 	b.gt	400a2c <_Z9TestBoundv+0x90>
  4009e8:	b9807fa0 	ldrsw	x0, [x29, #124]
  4009ec:	d37df000 	lsl	x0, x0, #3
  4009f0:	910083a1 	add	x1, x29, #0x20
  4009f4:	f8606822 	ldr	x2, [x1, x0]
  4009f8:	b9807fa0 	ldrsw	x0, [x29, #124]
  4009fc:	d37df000 	lsl	x0, x0, #3
  400a00:	910083a1 	add	x1, x29, #0x20
  400a04:	f8606820 	ldr	x0, [x1, x0]
  400a08:	f9400000 	ldr	x0, [x0]
  400a0c:	91004000 	add	x0, x0, #0x10
  400a10:	f9400001 	ldr	x1, [x0]
  400a14:	aa0203e0 	mov	x0, x2
  400a18:	d63f0020 	blr	x1
  400a1c:	b9407fa0 	ldr	w0, [x29, #124]
  400a20:	11000400 	add	w0, w0, #0x1
  400a24:	b9007fa0 	str	w0, [x29, #124]
  400a28:	17ffffed 	b	4009dc <_Z9TestBoundv+0x40>
  400a2c:	9100e3a0 	add	x0, x29, #0x38
  400a30:	940000b0 	bl	400cf0 <_ZN4Sub2D1Ev>
  400a34:	910143a0 	add	x0, x29, #0x50
  400a38:	940000c4 	bl	400d48 <_ZN4Sub1D1Ev>
  400a3c:	9101a3a0 	add	x0, x29, #0x68
  400a40:	94000044 	bl	400b50 <_ZN4BaseD1Ev>
  400a44:	1400000a 	b	400a6c <_Z9TestBoundv+0xd0>
  400a48:	aa0003f3 	mov	x19, x0
  400a4c:	9100e3a0 	add	x0, x29, #0x38
  400a50:	940000a8 	bl	400cf0 <_ZN4Sub2D1Ev>
  400a54:	910143a0 	add	x0, x29, #0x50
  400a58:	940000bc 	bl	400d48 <_ZN4Sub1D1Ev>
  400a5c:	9101a3a0 	add	x0, x29, #0x68
  400a60:	9400003c 	bl	400b50 <_ZN4BaseD1Ev>
  400a64:	aa1303e0 	mov	x0, x19
  400a68:	97ffff7e 	bl	400860 <_Unwind_Resume@plt>
  400a6c:	f9400bf3 	ldr	x19, [sp, #16]
  400a70:	a8c87bfd 	ldp	x29, x30, [sp], #128
  400a74:	d65f03c0 	ret

0000000000400a78 <main>:
  400a78:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400a7c:	910003fd 	mov	x29, sp
  400a80:	b9001fa0 	str	w0, [x29, #28]
  400a84:	f9000ba1 	str	x1, [x29, #16]
  400a88:	97ffffc5 	bl	40099c <_Z9TestBoundv>
  400a8c:	52800000 	mov	w0, #0x0                   	// #0
  400a90:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400a94:	d65f03c0 	ret

0000000000400a98 <_Z41__static_initialization_and_destruction_0ii>:
  400a98:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400a9c:	910003fd 	mov	x29, sp
  400aa0:	b9001fa0 	str	w0, [x29, #28]
  400aa4:	b9001ba1 	str	w1, [x29, #24]
  400aa8:	b9401fa0 	ldr	w0, [x29, #28]
  400aac:	7100041f 	cmp	w0, #0x1
  400ab0:	540001e1 	b.ne	400aec <_Z41__static_initialization_and_destruction_0ii+0x54>  // b.any
  400ab4:	b9401ba1 	ldr	w1, [x29, #24]
  400ab8:	529fffe0 	mov	w0, #0xffff                	// #65535
  400abc:	6b00003f 	cmp	w1, w0
  400ac0:	54000161 	b.ne	400aec <_Z41__static_initialization_and_destruction_0ii+0x54>  // b.any
  400ac4:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400ac8:	9101c000 	add	x0, x0, #0x70
  400acc:	97ffff59 	bl	400830 <_ZNSt8ios_base4InitC1Ev@plt>
  400ad0:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400ad4:	91016002 	add	x2, x0, #0x58
  400ad8:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400adc:	9101c001 	add	x1, x0, #0x70
  400ae0:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400ae4:	91224000 	add	x0, x0, #0x890
  400ae8:	97ffff4e 	bl	400820 <__cxa_atexit@plt>
  400aec:	d503201f 	nop
  400af0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400af4:	d65f03c0 	ret

0000000000400af8 <_GLOBAL__sub_I__Z9TestBoundv>:
  400af8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400afc:	910003fd 	mov	x29, sp
  400b00:	529fffe1 	mov	w1, #0xffff                	// #65535
  400b04:	52800020 	mov	w0, #0x1                   	// #1
  400b08:	97ffffe4 	bl	400a98 <_Z41__static_initialization_and_destruction_0ii>
  400b0c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400b10:	d65f03c0 	ret

0000000000400b14 <_ZN4BaseC1Ev>:
  400b14:	d10043ff 	sub	sp, sp, #0x10
  400b18:	f90007e0 	str	x0, [sp, #8]
  400b1c:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400b20:	913be001 	add	x1, x0, #0xef8
  400b24:	f94007e0 	ldr	x0, [sp, #8]
  400b28:	f9000001 	str	x1, [x0]
  400b2c:	f94007e0 	ldr	x0, [sp, #8]
  400b30:	52800021 	mov	w1, #0x1                   	// #1
  400b34:	b9000801 	str	w1, [x0, #8]
  400b38:	f94007e0 	ldr	x0, [sp, #8]
  400b3c:	52800041 	mov	w1, #0x2                   	// #2
  400b40:	b9000c01 	str	w1, [x0, #12]
  400b44:	d503201f 	nop
  400b48:	910043ff 	add	sp, sp, #0x10
  400b4c:	d65f03c0 	ret

0000000000400b50 <_ZN4BaseD1Ev>:
  400b50:	d10043ff 	sub	sp, sp, #0x10
  400b54:	f90007e0 	str	x0, [sp, #8]
  400b58:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400b5c:	913be001 	add	x1, x0, #0xef8
  400b60:	f94007e0 	ldr	x0, [sp, #8]
  400b64:	f9000001 	str	x1, [x0]
  400b68:	d503201f 	nop
  400b6c:	910043ff 	add	sp, sp, #0x10
  400b70:	d65f03c0 	ret

0000000000400b74 <_ZN4BaseD0Ev>:
  400b74:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400b78:	910003fd 	mov	x29, sp
  400b7c:	f9000fa0 	str	x0, [x29, #24]
  400b80:	f9400fa0 	ldr	x0, [x29, #24]
  400b84:	97fffff3 	bl	400b50 <_ZN4BaseD1Ev>
  400b88:	d2800201 	mov	x1, #0x10                  	// #16
  400b8c:	f9400fa0 	ldr	x0, [x29, #24]
  400b90:	97ffff20 	bl	400810 <_ZdlPvm@plt>
  400b94:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400b98:	d65f03c0 	ret

0000000000400b9c <_ZN4Base5printEv>:
  400b9c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400ba0:	910003fd 	mov	x29, sp
  400ba4:	f9000fa0 	str	x0, [x29, #24]
  400ba8:	f9400fa0 	ldr	x0, [x29, #24]
  400bac:	b9400801 	ldr	w1, [x0, #8]
  400bb0:	f9400fa0 	ldr	x0, [x29, #24]
  400bb4:	b9400c02 	ldr	w2, [x0, #12]
  400bb8:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400bbc:	91396000 	add	x0, x0, #0xe58
  400bc0:	97ffff30 	bl	400880 <printf@plt>
  400bc4:	d503201f 	nop
  400bc8:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400bcc:	d65f03c0 	ret

0000000000400bd0 <_ZN4Sub1C1Ev>:
  400bd0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400bd4:	910003fd 	mov	x29, sp
  400bd8:	f9000fa0 	str	x0, [x29, #24]
  400bdc:	f9400fa0 	ldr	x0, [x29, #24]
  400be0:	97ffffcd 	bl	400b14 <_ZN4BaseC1Ev>
  400be4:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400be8:	913b4001 	add	x1, x0, #0xed0
  400bec:	f9400fa0 	ldr	x0, [x29, #24]
  400bf0:	f9000001 	str	x1, [x0]
  400bf4:	f9400fa0 	ldr	x0, [x29, #24]
  400bf8:	52800081 	mov	w1, #0x4                   	// #4
  400bfc:	b9000801 	str	w1, [x0, #8]
  400c00:	f9400fa0 	ldr	x0, [x29, #24]
  400c04:	528000a1 	mov	w1, #0x5                   	// #5
  400c08:	b9000c01 	str	w1, [x0, #12]
  400c0c:	f9400fa0 	ldr	x0, [x29, #24]
  400c10:	528000c1 	mov	w1, #0x6                   	// #6
  400c14:	b9001001 	str	w1, [x0, #16]
  400c18:	d503201f 	nop
  400c1c:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400c20:	d65f03c0 	ret

0000000000400c24 <_ZN4Sub15printEv>:
  400c24:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400c28:	910003fd 	mov	x29, sp
  400c2c:	f9000fa0 	str	x0, [x29, #24]
  400c30:	f9400fa0 	ldr	x0, [x29, #24]
  400c34:	b9400801 	ldr	w1, [x0, #8]
  400c38:	f9400fa0 	ldr	x0, [x29, #24]
  400c3c:	b9400c02 	ldr	w2, [x0, #12]
  400c40:	f9400fa0 	ldr	x0, [x29, #24]
  400c44:	b9401003 	ldr	w3, [x0, #16]
  400c48:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400c4c:	9139a000 	add	x0, x0, #0xe68
  400c50:	97ffff0c 	bl	400880 <printf@plt>
  400c54:	d503201f 	nop
  400c58:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400c5c:	d65f03c0 	ret

0000000000400c60 <_ZN4Sub2C1Ev>:
  400c60:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400c64:	910003fd 	mov	x29, sp
  400c68:	f9000fa0 	str	x0, [x29, #24]
  400c6c:	f9400fa0 	ldr	x0, [x29, #24]
  400c70:	97ffffa9 	bl	400b14 <_ZN4BaseC1Ev>
  400c74:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400c78:	913aa001 	add	x1, x0, #0xea8
  400c7c:	f9400fa0 	ldr	x0, [x29, #24]
  400c80:	f9000001 	str	x1, [x0]
  400c84:	f9400fa0 	ldr	x0, [x29, #24]
  400c88:	528000e1 	mov	w1, #0x7                   	// #7
  400c8c:	b9000801 	str	w1, [x0, #8]
  400c90:	f9400fa0 	ldr	x0, [x29, #24]
  400c94:	52800101 	mov	w1, #0x8                   	// #8
  400c98:	b9000c01 	str	w1, [x0, #12]
  400c9c:	f9400fa0 	ldr	x0, [x29, #24]
  400ca0:	52800121 	mov	w1, #0x9                   	// #9
  400ca4:	b9001001 	str	w1, [x0, #16]
  400ca8:	d503201f 	nop
  400cac:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400cb0:	d65f03c0 	ret

0000000000400cb4 <_ZN4Sub25printEv>:
  400cb4:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400cb8:	910003fd 	mov	x29, sp
  400cbc:	f9000fa0 	str	x0, [x29, #24]
  400cc0:	f9400fa0 	ldr	x0, [x29, #24]
  400cc4:	b9400801 	ldr	w1, [x0, #8]
  400cc8:	f9400fa0 	ldr	x0, [x29, #24]
  400ccc:	b9400c02 	ldr	w2, [x0, #12]
  400cd0:	f9400fa0 	ldr	x0, [x29, #24]
  400cd4:	b9401003 	ldr	w3, [x0, #16]
  400cd8:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400cdc:	913a0000 	add	x0, x0, #0xe80
  400ce0:	97fffee8 	bl	400880 <printf@plt>
  400ce4:	d503201f 	nop
  400ce8:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400cec:	d65f03c0 	ret

0000000000400cf0 <_ZN4Sub2D1Ev>:
  400cf0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400cf4:	910003fd 	mov	x29, sp
  400cf8:	f9000fa0 	str	x0, [x29, #24]
  400cfc:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400d00:	913aa001 	add	x1, x0, #0xea8
  400d04:	f9400fa0 	ldr	x0, [x29, #24]
  400d08:	f9000001 	str	x1, [x0]
  400d0c:	f9400fa0 	ldr	x0, [x29, #24]
  400d10:	97ffff90 	bl	400b50 <_ZN4BaseD1Ev>
  400d14:	d503201f 	nop
  400d18:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400d1c:	d65f03c0 	ret

0000000000400d20 <_ZN4Sub2D0Ev>:
  400d20:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400d24:	910003fd 	mov	x29, sp
  400d28:	f9000fa0 	str	x0, [x29, #24]
  400d2c:	f9400fa0 	ldr	x0, [x29, #24]
  400d30:	97fffff0 	bl	400cf0 <_ZN4Sub2D1Ev>
  400d34:	d2800301 	mov	x1, #0x18                  	// #24
  400d38:	f9400fa0 	ldr	x0, [x29, #24]
  400d3c:	97fffeb5 	bl	400810 <_ZdlPvm@plt>
  400d40:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400d44:	d65f03c0 	ret

0000000000400d48 <_ZN4Sub1D1Ev>:
  400d48:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400d4c:	910003fd 	mov	x29, sp
  400d50:	f9000fa0 	str	x0, [x29, #24]
  400d54:	90000000 	adrp	x0, 400000 <_init-0x7c8>
  400d58:	913b4001 	add	x1, x0, #0xed0
  400d5c:	f9400fa0 	ldr	x0, [x29, #24]
  400d60:	f9000001 	str	x1, [x0]
  400d64:	f9400fa0 	ldr	x0, [x29, #24]
  400d68:	97ffff7a 	bl	400b50 <_ZN4BaseD1Ev>
  400d6c:	d503201f 	nop
  400d70:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400d74:	d65f03c0 	ret

0000000000400d78 <_ZN4Sub1D0Ev>:
  400d78:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400d7c:	910003fd 	mov	x29, sp
  400d80:	f9000fa0 	str	x0, [x29, #24]
  400d84:	f9400fa0 	ldr	x0, [x29, #24]
  400d88:	97fffff0 	bl	400d48 <_ZN4Sub1D1Ev>
  400d8c:	d2800301 	mov	x1, #0x18                  	// #24
  400d90:	f9400fa0 	ldr	x0, [x29, #24]
  400d94:	97fffe9f 	bl	400810 <_ZdlPvm@plt>
  400d98:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400d9c:	d65f03c0 	ret

0000000000400da0 <__libc_csu_init>:
  400da0:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400da4:	910003fd 	mov	x29, sp
  400da8:	a901d7f4 	stp	x20, x21, [sp, #24]
  400dac:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0xfd68>
  400db0:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0xfd68>
  400db4:	91340294 	add	x20, x20, #0xd00
  400db8:	9133c2b5 	add	x21, x21, #0xcf0
  400dbc:	a902dff6 	stp	x22, x23, [sp, #40]
  400dc0:	cb150294 	sub	x20, x20, x21
  400dc4:	f9001ff8 	str	x24, [sp, #56]
  400dc8:	2a0003f6 	mov	w22, w0
  400dcc:	aa0103f7 	mov	x23, x1
  400dd0:	9343fe94 	asr	x20, x20, #3
  400dd4:	aa0203f8 	mov	x24, x2
  400dd8:	97fffe7c 	bl	4007c8 <_init>
  400ddc:	b4000194 	cbz	x20, 400e0c <__libc_csu_init+0x6c>
  400de0:	f9000bb3 	str	x19, [x29, #16]
  400de4:	d2800013 	mov	x19, #0x0                   	// #0
  400de8:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400dec:	aa1803e2 	mov	x2, x24
  400df0:	aa1703e1 	mov	x1, x23
  400df4:	2a1603e0 	mov	w0, w22
  400df8:	91000673 	add	x19, x19, #0x1
  400dfc:	d63f0060 	blr	x3
  400e00:	eb13029f 	cmp	x20, x19
  400e04:	54ffff21 	b.ne	400de8 <__libc_csu_init+0x48>  // b.any
  400e08:	f9400bb3 	ldr	x19, [x29, #16]
  400e0c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400e10:	a942dff6 	ldp	x22, x23, [sp, #40]
  400e14:	f9401ff8 	ldr	x24, [sp, #56]
  400e18:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400e1c:	d65f03c0 	ret

0000000000400e20 <__libc_csu_fini>:
  400e20:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400e24 <_fini>:
  400e24:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400e28:	910003fd 	mov	x29, sp
  400e2c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400e30:	d65f03c0 	ret
